Design Verification Engineer

Location & Format:

Romania – Lasi or Bucharest.

Full-time office 5/2.

Project:

Company creates products, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems.

Role:

As Design Verification Engineer, you will join leading-edge team responsible for the verification of advanced interconnect systems in state-of-the-art microprocessors. This role focuses on ensuring the functionality, performance, and reliability of high-bandwidth data communication architectures.

Responsibilities:

• Perform pre-Silicon Verification of next generation high performance Microprocessor designs and related IPs;
• Develop, document and execute on verification test plans at unit level of design hierarchy;
• Develop high level language testbench components including stimulus drivers, behavioral models, monitors and checkers in SystemVerilog;
• Develop, simulate and debug directed/random stimulus to ensure design functionality according to specifications.

Required skills:

• Proficiency in SystemVerilog and UVM;
• 5+ years of relevant experience;
• Experience with formal verification techniques;
• Strong understanding of digital design and verification processes;
• Knowledge of interconnect or fabric architectures;
• Experience working in a Unix/Linux environment;
• English: B2 Upper Intermediate.

Nice to have:

• Familiarity with performance modeling;
• Background in Verilog and digital design;
• Experience with high-bandwidth interconnect protocols.