-I am working with external (Continental Automotive, Bosch, Cisco) and internal Freescale/NXP customers from wireless, networking and automotive business groups located in Arizona, Texas, China and Israel. -I am preparing Statement-of-Work (SOW), Spec documents and Test/Validation reports for IO IP blocks (LVCMOS, GPIO, DDR). I am gathering the technical requirements for IO interfaces from internal and external customers and working with the test and product engineers for quality evaluation of IO libraries. -I am working with third party IO IP blocks providers and external foundry partners (TSMC, SMIC, Samsung) regarding of all aspects of quality, yield and reliability issues of IO libraries and ESD protection networks. -As the I/O team Project manager, my obligations include the scheduling, project tracking, resource, risk, conflict management and quality audit/certification of I/O libraries. -Responsible for the Business Creation and Management (BCAM) Process, Quality Management System (QMS), 8D Analysis and CMMI certification of IO libraries for Automotive applications. -Also, my responsibilities include ESD protection/integration of IO cells, TLP and HBM/MM measurements, latch up issues, device and ICs reliability (burn-in, oxide breakdown and electromigration) in 45nm, 28nm, 16nm and 5nm CMOS/SOI/FinFet and SMARTMOS (Power LDMOS) technologies

-ESD design and optimization for high-performance CMOS ICs (the impact of CMOS technology scaling on ESD (gate-grounded NMOSFET, LVTSCR) robustness). ESD testing using TLP, HBM and MM test techniques. This is the research project with Gennum Corp., Canada. -The impact of CMOS technology scaling on reliability/quality and testing of sub-micron devices and CMOS ICs (for example, the effect of CMOS process variations on reliability and robustness of sub-0.18 um embedded SRAM cells). This is the research project with Philips Res. Lab., The Netherlands. - the optimization of current/logic and burn-in testing for high leaky CMOS technologies (for example, the estimation of effectiveness of bridging faults and gate oxide shorts detection in scaled down ISCAS-85/ 89 benchmark circuits using current/logic testing) - the yield loss, thermal management and thermal run away issues of burn-in testing (for example, the optimization of burn-in conditions (stress temperature and voltage) for high-performance circuits, such as microprocessors) This is the research project with Intel Microprocessor Res. Lab., USA. - The device and circuit design for reliability/quality and the analysis of leakage current components in sub-quarter micron CMOS technologies (for example, the layout optimization for gate induced drain leakage current reduction in deep sub-micron digital CMOS ICs).

- The JSC "Korona Semiconductor" had the product line for 0.8 um and 0.5 um CMOS technologies. During two years, I worked in this company as a senior process engineer. My main obligations were - to control the wet etching and cleaning of silicon wafers between CMOS technology steps using laminar flow wet benches and to manage the wet etching of aluminum metallization. - to manage the Spin-on Glass (SOG) Planarization.

The main obligations were the development of basic steps of BESOI technology - wet etching in solution of ethylenediamin-pyrocatechol-water - wafer bonding by thermal-compression fusion - chemical-mechanical polishing (CMP) - magnetron-sputtering and synthesis of a new glass-like dielectrics with thermal expansion coefficient close to the single crystal silicon, for example the multi-component glass dielectric based on BaO - Al2O3 - SiO2 - B2O3.